The present invention relates to the development of software timing models for integrated circuits. More specifically, the present invention provides methods and apparatus by which such timing models may be automatically generated for programmable logic devices (PLDs).
Circuit designers who use programmable logic devices to implement their designs typically revise and optimize their designs with exhaustive and detailed timing simulations. In order to perform such simulations, detailed and accurate characterization information regarding the loads presented by the device's interconnect structure must be provided by the PLD vendor. The interconnect structure of a PLD typically comprises a large number of intersecting conductors which enable the designer to electrically connect virtually any two points in the device. For a timing simulation to be useful, the propagation delay from each signal source to each signal destination must be accurately modeled.
In the past, PLDs were small enough so that a sufficiently accurate model for interconnect line delays was easily derived. For example, a linear formula might be used where the delay is proportional to the length of the interconnect signal path. Another approach simply used constants to represent the delay for particular lines. However, as the chips have become larger and more complex with smaller process geometries, the accuracy and therefore the sufficiency of these simplistic models has correspondingly decreased.
It will be understood that more sophisticated modeling of PLD interconnects may be and indeed has been accomplished. Unfortunately, the circuit density of the current PLD state of the art has made the development of such interconnect characterization models a very time intensive, and therefore very expensive procedure.
It is therefore desirable to develop techniques by which more sophisticated and accurate models of PLD interconnect lines may be generated. It is also desirable that such techniques enable the generation of such models more quickly than current techniques.